Traditional mixed-signal design verification is carried out separately by analog team who run transistor level simulation through different corners, and by digital team who run block simulation on RTL while using analog mixed-signal (AMS) behavior model to represent analog function. That method could not meet the verification requirements for advanced IP integrated SoC designs anymore. An integrated mixed-signal verification environment with Universal Verification Methodology (UVM) mixed-signal based testbench is introduced for subsystem verification, which supports different abstraction of analog design. In current work, traditional Verilog-AMS model was used first, followed by mixed mode AMS simulation in the same testbench in which analog IP was replaced with transistor level netlist to verify the possible missing points caused by inaccurate AMS model.
The simulation based on AMS model discovered 27% issues, while mixed mode AMS simulation found 73%, which can hardly be found at RTL synthesis or downstream flow thus lead to fatal silicon chip. Additionally, analog assertions are used to check the analog design function, to validate that the AMS model is correct through using the same testbench as means of model calibration, in order to deliver high quality AMS model to SoC design team for chip level simulation.